The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to devices and methods to protect input buffers low-voltage flash memory devices.
A transistor is a device that controls the flow of electrons. This ability to control the flow is important in that information, in the form of electricity, may be processed or stored by the transistor. To process or store greater amounts of information, transistors can be collected together to form an integrated circuit. An example of an integrated circuit that processes information is a central processing unit (CPU), which can be likened to the computing aspect of the human brain. Another example of an integrated circuit, which can be likened to the memorizing aspect of the human brain, is a memory device for storing information. A computer comprises these two core integrated circuitsxe2x80x94CPU and memory.
Memory devices have progressed from early designs, which consumed considerable power because of the need to continuously refresh the memory, to present devices, which are more desirable because of their frugal use of power. Presently, memory devices include low-voltage transistors. These low-voltage transistors use a voltage supply that is about 1.8 volts. Supplying too great a voltage to these low-voltage transistors, either by accident or design, would detrimentally affect the lifetime of these transistors.
Yet, voltage supplies larger than 1.8 volts exist in memory devices that include low-voltage transistors. Memory devices need these voltage supplies by design to perform memory operations, such as reading, programming, or erasing. In the event that a low-voltage transistor receives by accident an electrostatic discharge, voltages on the order of several thousand volts may undesirably enter and ruin the transistor. Such a lack of resistance by low-voltage transistors to higher voltages may lead to an eventual lack of acceptance in the marketplace for products based on memory devices that include such low-voltage transistors.
Thus, what is needed are devices and methods to inhibit the semiconductor breakdown that affects the lifetime of low-voltage transistors.
The above mentioned problems with low-voltage transistors and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Devices and methods are described which accord these benefits.
In one illustrative embodiment, a system is discussed to enhance buffering low-voltage flash memory. The system includes a multiple of thin gate-oxide transistors and an input buffer. The input buffer is receptive to an enabling signal, an input signal, and an inhibiting signal. The input buffer further includes a component that inhibits semiconductor and/or oxide breakdown of the plurality of thin gate-oxide transistors when the inhibiting signal is at a low voltage level.
In another illustrative embodiment, an input buffer for a low-voltage flash memory device is discussed. The input buffer includes an input stage and an output stage. The input buffer optionally includes a voltage sensor and an inhibiting circuit. The input stage has a transistor that includes a gate, a drain, and a source. The gate is receptive to an inhibiting signal. The drain is receptive to an input signal. The transistor inhibits the input signal from being presented at the source when the inhibiting signal is at a first predetermined level. The output stage has an inverter that includes first and second connections. The first connection is coupled to the source of the transistor. The second connection presents the input signal to the low-voltage flash memory device. The voltage sensor triggers when the input signal is at a second predetermined level. The voltage sensor is receptive to a pumped signal and the input signal. The inhibiting circuit selectively produces the inhibiting signal. The inhibiting circuit is receptive to a pumped signal and a sensed signal.
Another illustrative embodiment includes a method for buffering a low-voltage flash memory device. The method includes transferring and outputting. The act of transferring is executed by an input stage having a gate, a drain, and a source. The gate of the input stage is receptive to an inhibiting signal. The drain of the input stage is receptive to an input signal. The input stage inhibits the input signal from being presented at the source when the inhibiting signal is at a predetermined level. The act of outputting is executed by an output stage by inverting by an inverter. The inverter includes a first connection and a second connection. The first connection is coupled to the source of the input stage. The second connection presents the input signal to the low-voltage flash memory device.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.